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By John G. Webster (Editor)

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Example of synchronous circuit with feedback. A number of interesting and innovative examples of high-performance fully synchronous clock distribution networks have been developed for highly specialized and high-performance commercial processors and have been described in the literature. These VLSI-based systems required an unusual combination of methodologies and practices commensurate with large design teams while maintaining the localized circuit optimization requirements important to high-speed VLSI circuit design.

The layout process terminates when the root (or source) of the clock tree is reached. The schematic diagram of this geometric matching process is illustrated in CLOCK DISTRIBUTION IN SYNCHRONOUS SYSTEMS Figure 17. Geometric matching to create zero clock skew. Fig. 17. Thus, the automated layout algorithm attempts to balance the delay of each clock branch in a recursive manner, moving from the leaves to the root of the tree. The appropriate branching points of the zero-skew subtree are chosen so as to maintain equal delay.

In Refs. 108–110, the automated layout of the clock tree is composed of a two-phase process. The clock net is initially routed in a binary-tree manner with the clock pins as leaf nodes and the clock buffer as the root. This layout phase is followed by a post-layout phase in which the clock nets are widened according to the zero-skew specifications, thereby giving the clock layout system additional flexibility in routing around possible blockages. The choice of which clock net to widen is determined by analyzing the sensitivity of the clock net impedance.

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64.VLSI Systems by John G. Webster (Editor)

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